The present invention relates generally to a MIS semiconductor device and a method of fabricating the same, and more particularly to improvements of a source region and a drain region.
In order to meet a demand for a higher performance based on a higher integration density achieved by modern finer processing, when semiconductor integrated circuits (ICs) are fabricated, a gate electrode of a transistor is processed with a highest possible level of lithographic processing. Because of this, a variance occurs among gate electrodes and it leads to a variance in channel length and thus to a greater variance in transistor characteristics. Consequently, the product yield decreases. On the other hand, with miniaturization of semiconductor ICs, fine transistors and wiring are arranged very dense and the length of wiring increases. Even if the operation speed of transistors is to be increased based on the miniaturization, this cannot be achieved due to a parasitic capacitance and resistance between transistors and wiring.
FIG. 1 shows a structure of a conventional flat-type transistor. A gate electrode 3 is formed on a silicon substrate 1, with a gate insulation film 2 interposed. Wiring elements 4a, 4b are formed on both sides of the gate electrode 3, with an insulation film 9 interposed. A source diffusion layer 5a and a drain diffusion layer 5b are formed within the silicon substrate 1. A region 6 between the diffusion layers 5a and 5b serves as a channel region. Numeral 7 denotes a device isolating insulation film, and numeral 8 an interlayer insulation film 8.
Since the diffusion layers 5a and 5b are arranged adjacent to the channel region 6 within the silicon substrate 1, this arrangement weakens a control power with which the gate electrode 3 controls the channel region 6, and a so-called short-channel effect occurs. Consequently, the influence of a variation in lithographic processing increases.
For comparison with problems of a concave-type transistor and other conventional transistors, which will be described later, FIG. 1 shows an electric current indicated by a dot-and-dash line in FIG. 1, which is produced when the flat-type transistor is operated. A current injected from the wiring element 4a enters the source diffusion layer 5a and then its accumulation layer (corresponding to a surface portion of the diffusion layer 5a, which is opposed to the gate electrode 3 with the gate insulation film 2 interposed, and having a carrier density several tens of times as high as the active impurity concentration in the diffusion layer). The current then flows into an inversion layer of the channel region 6 and into the wiring element 4b via an accumulation layer of the drain diffusion layer 5b and a diffusion region outside the accumulation layer. The current path is thus formed.
In the diffusion region outside the accumulation layer, a high-carrier-density region on the surface of the substrate 1 is lost, and the current flows deep into the diffusion layers 5a and 5b due to the carrier density determined by the active impurity concentration, and a so-called spreading resistance occurs. However, as indicated by a dot-and-dash line in FIG. 1, a substantially linear current path is formed.
Normally, the source and drain regions are formed such that impurities of a conductivity type opposite to the conductivity type of the substrate are ion-implanted, with the gate electrode used as a mask, and the impurities are activated or diffused by a heating process. The source region and drain region serve to connect the channel with the current paths to the wiring elements. In order to effect the connection with a sufficiently low resistance value, a deep region with high concentration needs to be formed by diffusion.
FIG. 2 shows a relationship between an electron concentration distribution and impurities in the drain diffusion region 5b at the time the flat-type transistor having a gate length of 0.1 xcexcm is operated. FIG. 2 shows, by device simulation, the area near the gate electrode 3 in FIG. 3. FIG. 2 shows only the area on the side of the drain diffusion layer 5b. In this simulation, 1V is applied to the gate electrode 3, and 1V is applied to the drain diffusion layer 5b. 
A bias voltage applied to the source diffusion layer 5a is 0V. Thus, the current in the region near the source diffusion layer 5a is strongly influenced by the gate bias. In the vicinity of the drain diffusion layer 5b, the influence exerted on the surface of the substrate 1 by the gate electrode 3 is weaker than in the case of the source diffusion layer 5a, because of the bias voltage applied to the drain diffusion layer 5b. However, since the gate insulation film 2 is very thin, the current even near the drain diffusion layer 5b is strongly influenced by the gate electrode 3. The following description is mainly directed to the drain diffusion layer 5b, but the relationship between the electron density/current density distribution and the position of the gate electrode 3 or the diffusion layer impurity distribution is basically applicable to the source diffusion layer 5a. 
The drain diffusion layer 5b extends to a location below or inside the gate electrode 3 to effect connection with the channel, thus forming a pn junction with channel impurities. The position of the pn junction is indicated by a bold line in FIG. 2. At the position of the pn junction, impurities of opposite conductivity types cancel each other and the net impurity concentration becomes substantially zero.
Specifically, even if high-concentration impurities of about 1xc3x972020 cmxe2x88x923 are introduced in the drain diffusion layer 5b, as indicated by a broken line in FIG. 2, the impurity concentration in the vicinity of the edge of the gate electrode 3 generally decreases due to diffusion, and the impurity concentration in the region away from the edge near the center of the channel region further decreases toward the pn junction. A depletion layer forms near the junction, and the carrier concentration (electron density) is very low. Thus, the source diffusion layer 5a or drain diffusion layer 5b is electrically isolated from the substrate 1 of the opposite conductivity type. In FIG. 2, an electron density distribution curve represented by log10 (electron density)=18 is away from the junction plate, compared to an impurity concentration distribution curve represented by log10 (impurity concentration)=18. As is understood from this, the carrier density (electron density) is lower than the impurity concentration in the vicinity of the junction in the region of the drain diffusion layer 5b away from the surface of the substrate 1.
When the transistor is operated, an inversion layer is formed in the surface portion of substrate 1 in the channel region 6 by the voltage applied to the gate electrode 3. In FIG. 2, the region with high electron density at the surface portion of the channel region 6 is this inversion layer. On the other hand, an accumulation layer is formed in the drain diffusion layer 5b near the junction in the vicinity of the surface of the substrate 1. This accumulation layer joins the inversion layer formed in the channel region 6 in the vicinity of the junction, thus forming a current path.
In FIG. 2, it is this accumulation layer where the electron density is higher than the impurity concentration in the drain diffusion layer near the junction plane in the vicinity of the surface of the substrate 1. In the region of the drain diffusion layer 5b, which is away from the edge of the gate electrode 3 and has a high impurity concentration, the electron density is equal to the impurity concentration.
FIG. 3 shows a relationship between a current density distribution and the position of the gate electrode 3 or the impurity concentration distribution, when the same bias is applied to the same MOS transistor as in FIG. 2. On the inside region of the edge of the gate electrode 3, a region with high current density is provided near the surface of the substrate 1 by the formation of the inversion layer at the surface of the channel region 6 or the formation of the accumulation layer at the surface of the impurity region. However, on the outside of the edge of the gate electrode 3, the intensity of the electric field due to the gate electrode 3 sharply decreases. As a result, the region with high current density, biased toward the surface of the substrate 1, is lost. In addition, a low current density is distributed deep into the substrate along the region with high electron density in the drain diffusion layer 5b. 
Accordingly, in the region outside the edge of the gate electrode 3, where the influence of the gate bias is small, the parasitic resistance cannot be lowered by forming an adequate accumulation layer with induction by the gate bias. Instead, it is necessary to sufficiently increase the carrier concentration determined by the impurity concentration and to form the impurity region deep into the substrate 1 in accordance with its concentration, thereby to decrease the resistance. In other words, when the parasitic resistance in the region outside the edge is to be decreased, it is imperative to sufficiently increase the impurity concentration below the edge of the gate electrode 3 and to distribute the high-impurity concentration region deep into the substrate 1.
The results shown in FIGS. 2 and 3 are of typical planer type MIS transistors. The electron density distribution and the current density distribution will vary in accordance with the impurity distribution in the drain diffusion layer or in accordance with the position of the gate electrode edge, the shape of the gate electrode near the edge, etc. In some cases, the peak position of the electron density distribution and/or current density distribution may lie not at the surface of the substrate but at a location deep in the substrate. In such cases, too, the parasitic resistance in the diffusion layer below the edge is decreased by forming an accumulation layer at the surface of the diffusion layer with the electric field of the gate electrode.
The impurity region inside the edge of the gate electrode 3 is indispensable to sufficiently increase the impurity concentration below the edge of the gate electrode 3 and to distribute the high impurity concentration deep into the substrate 1. However, due to modern miniaturization, the length of the gate electrode 3 is extremely reduced and the electric field due to the impurity distribution in the diffusion layer 5a, 5b, which is applied to the channel region 6, weakens the field applied by the gate electrode 3 to the channel region 6. Consequently, a so-called short-channel effect occurs and the yield of products further decreases.
In order to suppress the short-channel effect, efforts have been made to reduce the depth of the junction of the diffusion layer 5a, 5b. As stated above, however, in order to connect the channel region 6 and the high-impurity-concentration region in the drain diffusion layer 5b with a sufficiently low parasitic resistance, it is imperative to sufficiently increase the impurity concentration below the edge of the gate electrode 3 and to distribute the high impurity concentration deep into the substrate 1. This contradicts the purpose of suppressing the short-channel effect.
A concave-type transistor was proposed as a structure for eliminating this contradiction (see, e.g. Nishimatsu et al., Groove Gate MOSFET, 8th Conf. On Solid State Device, pp. 179-183, 1976). FIG. 4A is a cross-sectional view showing a conventional concave-type transistor structure. The structural elements common to those in FIG. 1 are denoted by like reference numerals. In the conventional concave-type transistor, a source diffusion layer 45a and a drain diffusion layer 45b are formed at a level higher than the surface of a channel region formed at a bottom of a concave portion. Thereby, the influence of an impurity distribution in the diffusion layers 45a and 45b, which acts upon the control performance of a gate electrode 43 which electrically controls the channel region, is suppressed. In the concave-type transistor, the source and drain can be formed thick (deep) with a distance being kept from the channel region at the concave bottom. Thus, while the short-channel effect is being suppressed, the parasitic resistance per unit length in the source and drain diffusion layer portions can be reduced.
The ordinary concave-type transistor, however, has the following problems. FIG. 4B is an enlarged view of a main portion of the concave-type transistor in FIG. 4A. An inversion layer 46 is formed at a concave bottom surface of the silicon substrate 1, an inversion layer 47 is formed at a concave side face, and an accumulation layer 48 is formed at a concave side face in a surface portion of the diffusion layer 45a which is in contact with a gate insulation film 42. The inversion layer 46 at the concave bottom surface corresponds to the inversion layer formed at the surface portion of the channel region 46 of the flat-type transistor shown in FIG. 1.
As described above, in the ordinary concave-type transistor, in addition to the inversion layer 46 at the concave bottom surface, those regions are provided on the concave side faces, where the side channel portions and the source and drain diffusion layers 45a and 45b continuous thereto are parallel to the gate electrode 43 with the gate insulation film 42 interposed. In the region at the concave side face which is parallel to the gate electrode 43, the inversion layer 47 at the concave side face and the accumulation layer 48 at the concave side face are formed in parallel to the side face of the gate electrode 43 to constitute a current path. Consequently, a large parasitic capacitance occurs.
Comparing the current path of the flat-type transistor shown in FIG. 1 with that of the concave-type transistor shown in FIG. 4, the current path of the flat-type transistor is linear whereas the current path of the concave transistor has acute angles with the concave bottom face and the concave side face. Thus, the length of the current path to the wiring element 4a, 4b connected to the diffusion layer 45a, 45b is increased.
In normal cases, the parasitic capacitance between the gate electrode 43, or the wiring element connected to the gate electrode 43, and the wiring element 4a, 4b is suppressed, or a leak current occurring therebetween is suppressed in the following manner. That is, the distance between the gate electrode 43 and the wiring element 4a, 4b to the diffusion layer 45a, 4tb, is increased, or a side-wall insulation film 49 or a non-conductive film region is formed in contact with the gate side face on the substrate 1.
In the case of the ordinary concave-type transistor wherein the bottom surface of the side-wall insulation film 49 and the concave bottom surface are parallel, a current path having portions with nearly acute angles are formed between stepped planes of the bottom surface of the side-wall insulation film 49 and the concave bottom surface. Consequently, as compared to the case of the above-described flat-type transistor, the length of the current path increases and the parasitic resistance also increases.
In the channel periphery region, a carrier distribution peak appears in a very thin region of 0.01 xcexcm along the channel surface. Accordingly, when the current path with nearly acute angles, i.e. the path of electrons, is present near the channel bottom surface, an excess work is required for carriers to follow an acute-angle peak distribution and the current value decreases.
On the other hand, xe2x80x9cUltra-Shallow in-situ-doped raised source/drain structure for sub-tenth micron CMOSxe2x80x9d, Y. Nakahara et al., pp. 174-175, 1996 Symposium on VLSI Technology Digest of Technical Papers, shows a transistor structure having a source region and a drain region with an oblique substrate surface as a conventional structure of a p-type flat-type transistor. This structure is shown in FIG. 5. The structure shown in FIG. 5 differs from that of the concave-type structure shown in FIG. 4 in that the channel region and the source/drain are formed in a flat shape. A current reaches the wiring (not shown) to the source and drain via shallow diffusion layers 55a and 55b and high-density, deep diffusion layers 55c and 55d which are in the same plane as the channel region.
Specifically, in the concave-type transistor shown in FIG. 4B, the accumulation layer 48 continuous with the inversion layer in the channel region is shallower than the channel bottom face, and thereby the diffusion layers 45a and 45b are situated apart from the channel bottom face. Thus, the short-channel effect is reduced. On the other hand, in the structure shown in FIG. 5, the accumulation layers formed in the source diffusion layer and drain diffusion layer continuous with the channel inversion layer are formed in the same plane as the inversion layer of the channel region at end portions adjacent to the channel regions of shallow diffusion layers 55a and 55b. Consequently, shallow layers 55a and 55b in FIG. 5 extend in the silicon substrate 1, adjoining the channel inversion layers, and the short-channel effect may occur depending on their thickness. In order to suppress the short-channel effect, very shallow source diffusion layer 55a and drain diffusion layer 55b are formed adjacent to the channel region with use of silicon. The thickness of the diffusion layers 55a and 55b is compensated by forming an epitaxial source diffusion layer 55e and a drain diffusion layer 55f on the silicon substrate 1. The edges of the gate electrode 53 are situated apart from the surfaces of the epitaxial diffusion layers 55e and 55f, with a nitride side wall 56 interposed, and over the shallow source diffusion layer 55a and drain diffusion layer 55b. 
By virtue of this structure, while the transistor is being operated, a less influence is exerted by the electric field of the gate electrode 53 upon the current path formed in the epitaxial diffusion layers 55e and 55f. Accordingly, the current flows to wide regions in the epitaxial diffusion layers 55e and 55f with a spreading resistance. Current paths, however, are provided in parallel to the diffusion layers 55a and 55b, and a parasitic resistance of the entire source and drain is decreased.
In other words, the epitaxial diffusion layers 55e and 55f in the structure shown in FIG. 5 advantageously function to reduce the high resistance in the shallow diffusion layer 55a, 55b reading the deep, high-density diffusion layer 55c, 55d formed in the same plane as the channel bottom surface, by compensating the thickness of these regions.
Besides, since the surfaces of the epitaxial diffusion layers 55e and 55f have oblique portions, a thick oxide side wall 57 can be formed between the gate electrode 53 and the surface of the source/drain diffusion layer, with the nitride side wall 56 interposed. The parasitic capacitance is thus reduced.
However, since this transistor structure is of the flat type, the short-channel effect cannot fully be suppressed merely by controlling the thickness of the shallow diffusion layer 55a, 55b. 
As has been described above, when the conventional semiconductor apparatus is used, it is not possible to suppress the short-channel effect, to reduce the parasitic capacitance or resistance, or to decrease the resistance of the current path.
The present invention has been made in consideration of the above problems, and its object is to provide a semiconductor device and a method of fabricating the same, wherein a parasitic resistance and a parasitic capacitance are reduced and a short-channel effect is suppressed.
In order to achieve the above object, according to an aspect of the invention, there is provided a MIS type semiconductor device comprising:
a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion;
a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed;
a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer; and
wiring contact portions for contact with the surface of the semiconductor layer,
wherein an edge of the gate electrode is located inside the recess portion provided in the semi-conductor layer, and there is provided at least one of a mutually opposed portion between the gate electrode and the source region and a mutually opposed portion between the gate electrode and the drain region, whereby at least one of a portion of the source region and a portion of the drain region, which lie in the associated mutually opposed portions, functions as an accumulation layer.
According to another aspect of the invention, there is provided a MIS type semiconductor device comprising:
a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion;
a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed;
a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer; and
a channel region formed under the bottom of the recess portion of the semiconductor layer,
wherein the source region and the gate electrode have a first mutually opposed region at a first position of a junction between the source region and the channel region in the vicinity of the gate insulating film,
the drain region and the gate electrode have a second mutually opposed region at a second position of a junction between the drain region and the channel region in the vicinity of the gate insulating film,
one of the source region and the drain region, which lies in at least one of the first and second mutually opposed regions functions as an accumulation layer, and
a portion of the insulating film between the gate electrode and at least one of the source region and the drain region, which lies outside an associated one of the first and second mutually opposed regions, is made thicker than the associated one of the first and second mutually opposed regions.
According to still another aspect of the invention, there is provided a MIS type semiconductor device comprising:
a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion;
a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed;
a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer; and
a channel region formed under the bottom of the recess portion of the semiconductor layer,
wherein the source region and the gate electrode have a first mutually opposed region at a first position of a junction between the source region and the channel region in the vicinity of the gate insulating film,
the drain region and the gate electrode have a second mutually opposed region at a second position of a junction between the drain region and the channel region in the vicinity of the gate insulating film,
one of the source region and the drain region, which lies in at least one of the first and second mutually opposed regions functions as an accumulation layer,
a portion of the insulating film between the gate electrode and one of the source region and the drain region, which lies outside an associated one of the first and second mutually opposed regions, is made thicker than the associated one of the first and second mutually opposed regions, and
contact portions are provided on surfaces of the source region and the drain region at a distance from the gate electrode, a current path is formed between the source region and the associated one of the contact portions and between the drain region and the other contact portion along a boundary plane between the insulating film and the source and drain regions, and a distance between each of the contact portions and the gate electrode is less than 1.5 times the width of the gate electrode.
According to still another aspect of the invention, there is provided a method of manufacturing a MIS type semiconductor device, the method comprising the steps of:
forming a recess portion having a side wall with an obtuse angle in a semiconductor layer by an RIE process;
forming a gate insulating film covering a surface of the semiconductor layer;
forming a conductive film on the gate insulating film including the recess portion; and
patterning the conductive film by a lithographic process such that the side wall is located at a side surface of the recess portion, thereby forming a gate electrode.
According to still another aspect of the invention, there is provided a method of manufacturing a MIS type semiconductor device, the method comprising:
laminating a first insulating film and a dummy gate selectively on a first semiconductor layer;
selectively growing a semiconductor material in a solid phase, with the dummy gate used as a mask, thereby forming a second semiconductor layer with an obtuse-angled side wall, the second semiconductor layer sandwiching the dummy gate;
removing the first insulating film and the dummy gate; and
forming a gate insulating film and a gate electrode in succession selectively in a region where the first insulating film and the dummy gate have existed.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.